Functional Verification of Large-integers Circuits using a Cosimulation-based Approach

Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer’s functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability

Détection automatique de chutes de personnes basée sur des descripteurs spatio-temporels (définition de la méthode, évaluation des performances et implantation temps-réel)

Nous proposons une méthode supervisée de détection de chutes de personnes en temps réel, robusteaux changements de point de vue et d environnement. La première partie consiste à rendredisponible en ligne une base de vidéos DSFD enregistrées dans quatre lieux différents et qui comporteun grand nombre d annotations manuelles propices aux comparaisons de méthodes. Nousavons aussi défini une métrique d évaluation qui permet d évaluer la méthode en s adaptant à la naturedu flux vidéo et la durée d une chute, et en tenant compte des contraintes temps réel. Dans unsecond temps, nous avons procédé à la construction et l évaluation des descripteurs spatio-temporelsSTHF, calculés à partir des attributs géométriques de la forme en mouvement dans la scène ainsique leurs transformations, pour définir le descripteur optimisé de chute après une méthode de sélectiond attributs. La robustesse aux changements d environnement a été évaluée en utilisant les SVMet le Boosting. On parvient à améliorer les performances par la mise à jour de l apprentissage parl intégration des vidéos sans chutes enregistrées dans l environnement définitif. Enfin, nous avonsréalisé, une implantation de ce détecteur sur un système embarqué assimilable à une caméra intelligentebasée sur un composant SoC de type Zynq. Une démarche de type Adéquation AlgorithmeArchitecture a permis d obtenir un bon compromis performance de classification/temps de traitementWe propose a supervised approach to detect falls in home environment adapted to location andpoint of view changes. First, we maid publicly available a realistic dataset, acquired in four differentlocations, containing a large number of manual annotation suitable for methods comparison. We alsodefined a new metric, adapted to real-time tasks, allowing to evaluate fall detection performance ina continuous video stream. Then, we build the initial spatio-temporal descriptor named STHF usingseveral combinations of transformations of geometrical features and an automatically optimised setof spatio-temporal descriptors thanks to an automatic feature selection step. We propose a realisticand pragmatic protocol which enables performance to be improved by updating the training in thecurrent location with normal activities records. Finally, we implemented the fall detection in Zynqbasedhardware platform similar to smart camera. An Algorithm-Architecture Adequacy step allowsa good trade-off between performance of classification and processing timeDIJON-BU Doc.électronique (212319901) / SudocSudocFranceF

System level modeling methodology of NoC design from UML-MARTE to VHDL

International audienceThe evolution of the semiconductor technology caters for the increase in the System-on-Chip (SoC) complexity. In particular, this complexity appears in the communication infrastructures like the Network-on-Chips (NoCs). However many complex SoCs are becoming increasingly hard to manage. In fact, the design space, which represents all the concepts that need to be explored during the SoC design, is becoming dramatically large and difficult to explore. In addition, the manipulation of SoCs at low levels, like the Register Transfer Level (RTL), is based on manual approaches. This has resulted in the increase of both time-to-market and the development costs. Thus, there is a need for developing some automated high level modeling environments for computer aided design in order to handle the design complexity and meet tight time-to-market requirements. The extension of the UML language called UML profile for MARTE (Modeling and Analysis of Real-Time and Embedded systems) allows the modeling of repetitive structures such as the NoC topologies which are based on specific concepts. This paper presents a new methodology for modeling concepts of NoC-based architectures, especially the modeling of topology of the interconnections with the help of the repetitive structure modeling (RSM) package of MARTE profile. This work deals with the ways of improving the effectiveness of the MARTE standard by clarifying and extending some notations in order to model complex NoC topologies. Our contribution includes a description of how these concepts may be mapped into VHDL. The generated code has been successfully evaluated and validated for several NoC topologies

FERONOC : FLEXIBLE AND EXTENSIBLE ROUTER IMPLEMENTATION FOR DIAGONAL MESH TOPOLOGY

International audienceNetworks on Chip (NoCs) can improve a set of perfor- mances criteria, in complex SoCs, such as scalability, flexibility and adaptability. However, performances of a NoC are closely related to its topology. The diameter and average distance represent an important factor in term of performances and implementation. The proposed diagonal mesh topology is designed to offer a good tradeoff between hardware cost and theoretical quality of service (QoS). It can contain a large number of nodes without changing the maximum diameter which is equal to 2. In this paper, we present a new router architecture called FeRoNoC (Flexible, extensible Router NoC) and its Register Transfer Level (RTL) hardware implementation for the diagonal mesh topology. The architecture of our NoC is based on a flexible and extensible router which consists of a packet switching technique and deterministic routing algorithm. Effectiveness and performances of the proposed topology have been shown using a virtex5 FPGA implementation. A comparative performances study of the proposed NoC architecture with others topology is performed

Modeling Networks-on-Chip at System Level with the MARTE UML profile

International audienceThe study of Networks on Chips (NoCs) is a research field that primarily addresses the global communication in Systems-on-Chip (SoCs). The selected topology and the routing algorithm play a prime role in the performance of NoC architectures. In order to handle the design complexity and meet the tight time-to-market constraints, it is important to automate most of these NoC design phases. The extension of the UML language called UML profile for MARTE (Modeling and Analysis of Real-Time and Embedded systems) specifies some concepts for model-based design and analysis of real time and embedded systems. This paper presents a MARTE based methodology for modeling concepts of NoC based architectures. It aims at improving the effectiveness of the MARTE standard by clarifying some notations and extending some definitions in the standard, in order to be able to model complex architectures like NoCs

Définition et implantation matérielle d'un estimateur de mouvement configurable pour la compression vidéo adaptative

L objectif de cette thèse est la conception d une plateforme de compression vidéo de nouvelle génération à haut degré d adaptation vis-à-vis de l environnement. Ce besoin d adaptabilité a plusieurs origines. D une part les systèmes actuels visent à s adapter à la diversité et l hétérogénéité des médias et des terminaux actuels. D autre part, l exploitation de l information contenue dans une scène vidéo dépend de l application visée et des besoins des utilisateurs. Ainsi, l information peut être exploitée de manière complètement inhomogène spatialement ou temporellement. En effet, l exploitation spatiale de la scène peut être irrégulière par définition, par la définition automatique ou manuelle de zones d intérêts dans l image. La qualité de la vidéo, donc de la compression, doit pouvoir s adapter afin de limiter la quantité de donnée à transmettre. Cette qualité est donc dépendante de l évolution de la scène vidéo elle-même. Une architecture matérielle configurable a été proposée dans cette thèse permettant de supporter différents algorithmes de recherche en offrant une précision subpixélique.La synthèse des travaux menés dans ce domaine et la comparaison objective des résultats obtenus par rapport à l'état de l'art. L architecture proposée est synthétisée à base d un FPGA Virtex 6 FPGA, les résultats obtenus pourraient traiter l'estimation du mouvement pixélique avec un flux vidéo haute définition (HD 1080), respectivement à 13 images par seconde en utilisant la stratégie de recherche exhaustive (108K Macroblocs/s) et jusqu'à 223 images par seconde avec la recherche selon un grille en diamant (1,8 M Macroblocs /s). En outre le raffinement subpixélique en quart-pel est réalisé à Macroblocs 232k/ sThe aim of this thesis was to define and implement a hardware architecture of a configurable motion estimation capable of supporting various search strategies with the desired accuracy for adaptive video compression. This need for adaptability had several origins. Firstly, the current systems are designed to adapt to the diversity and heterogeneity of current terminals and media. Secondly, the use of information contained in a video scene depends on the intended applications and user needs. This objective scoring modestly in the challenge offered by the development of digital video requires a faster processing and a high compression ratio.In this thesis, a flexible hardware implementation of the motion estimator which enables the integer motion search algorithms to be modified and the fractional search as well as variable block size to be selected and adjusted. Hence, this novel architecture, especially designed for FPGA targets, proposes high-speed processing for a configuration which supports the variable size blocks and quarter-pelrefinement, as described in H.264. The proposed low-cost architecture based on Virtex 6 FPGA canprocess integer motion estimation on 1080 HD video streams, respectively, at 13 fps using full search strategy (108k Macroblocks/s) and up to 223 fps using diamond search (1.8M Macroblocks/s). Moreover subpel refinement in quarter-pel mode is performed at 232k Macroblocks/sDIJON-BU Doc.électronique (212319901) / SudocSudocFranceF

AN EXHAUSTIVE ANALYSIS OF SEU EFFECTS IN THE SRAM MEMORY OF SOFT PROCESSOR

The Embedded system design is characterized by its daily complexity. It integrates a hardware and software parts together on a common platform. These parts may be defective by a spurious signal, subsequently found to be two types of errors. The software and hardware errors can attack the embedded system. In this paper an exhaustive analysis of the effects of Single Event Upset into the Static Random Access Memory occupied area of Aeroflex Gaisler LEON3 processor is presented. It is a soft core pipeline processor that is part of the GRLIB IP library based on Scalable Processor Architecture, SPARC V8,implemented in Virtex-5 FPGA. A new software methodology allowing fault injection is explored and illustrated in order to classify the defective behaviours while executing several benchmarks. This investigation is done by an exhaustive fault injection campaign (More than 200000 transient faults) into SRAM memory of LEON3 considered as a processor. The proposed method makes error rate predictions more accurate compared to other techniques